The present invention relates to systems for decoding coded video information. More specifically, the invention relates to microarchitectures of hardware cores for performing MPEG-2 decoding.
As digital processing systems have become faster and endowed with greater throughput and storage capacity, it has become apparent that integrated circuits, at least those specifically designed for the task, could reconstruct compressed digital video information to provide good quality video display. In the late 1980s, a digital video reconstruction standard known as "MPEG" (for Motion Pictures Experts Group) was promulgated by the International Standards Organization (ISO). MPEG video syntax provides an efficient way to represent image sequences in the form of compact coded data.
MPEG also defines the form of an unambiguously compressed bit stream generated for digital video data. Given knowledge of the MPEG rules, one can design a decoder which reconstructs a video sequence from the compressed bit stream. The first version of MPEG (MPEG-1) was optimized to handle data at a rate of 1.5 Mbits/second and reconstruct video frames at 30 Hz, with each frame having a resolution of 352 pixels by 240 lines in the case the NTSC video standard and 352 pixels by 288 lines in the case of the PAL video standard. Decoded MPEG-1 video can approximate the perceptual quality of consumer video tape (VHS).
MPEG-2 was initiated in the early 1990s to define a syntax for efficient representation of broadcast video. With the MPEG-2 standard, frames of 720 pixels/line by 480 lines (NTSC) or 720 pixels/line by 576 lines (PAL) are displayed at 30 Hz. The MPEG-2 decoding algorithms require certain steps such as inverse scan, inverse quantization, inverse discrete cosine transform, half pel (or half pixel) compensation, merge prediction and error, motion vector decoding, variable length decoding, and run level decoding. All of these functions are described in the ISO's MPEG-2 standard Document ISO/IEC 13818-2: 1995(E) (hereinafter "the ISO/MPEG-2 Document"). That document is incorporated herein by reference for all purposes.
Hereinafter, except where distinctions between the two versions of the MPEG standard exist, the terms "MPEG," "MPEG-1," and "MPEG-2" will be used interchangeably to reference those video decoding algorithms promulgated in the original MPEG-1 Document as well as in the MPEG-2 Document, and any future versions of MPEG decoding.
While CPU digital processing power has improved markedly in recent years, the shear volume of encoded/compressed data that must be decompressed and displayed at 30 Hz generally requires that some system hardware, beyond the CPU, be dedicated to MPEG-2 decoding. CPUs like SPARC from Sun Microsystems, Inc. of Mountain View, Calif., MIPS from Silicon Graphics, Inc. of Mountain View, Calif., Pentium from Intel Corporation of Santa Clara, Calif., etc. can not, in themselves, handle MPEG-2 decoding. Thus, software/firmware implementation of the MPEG-2 decoding algorithm is not yet practical for mass market consumer applications, and dedicated hardware must be employed to perform at least some MPEG-2 decoding functions.
While the ISO/MPEG-2 standard does specify the form that encoded video data must take, it does not specify either the exact sequence of steps or the hardware for decoding the data. Thus, designers of MPEG-2 decoding systems are free to provide their own designs for particular applications. In fact it is expected that each time an MPEG-2 decoder is to be designed for a new application, a designer will generate a new integrated circuit layout for the decoder.
Various MPEG-2 decoder chips are now available including the HDM8211M (from Hyundai Corporation of Seoul Korea) full MPEG-2 decoder of audio, video, and system (transport) bitstreams. See Bursky, "Single Chip Performs Both Audio and Video Decoding" Electronic Design, Apr. 3, 1995, pp. 77-80. This integrated circuit includes an MPEG-2 video decoder, an audio decoder, a system stream demultiplexer (this block separates the video and audio streams), a video display, a DRAM controller, and a 32-bit RISC processor (licensed from the SPARC Technology Business Group) which controls the internal workings of the MPEG-2 chip.
Designing new MPEG-2 decoder hardware such as the above described HDM8211M is, of course, a quite expensive process. The design is first provided as a Boolean description in a hardware design language such as Verilog. Then the code for the processor design model is used to create a net list, which is, in turn, used to create a physical layout for the integrated circuit. The physical layout must then converted to reticles (or masks) for fabricating the ultimate silicon version of the integrated circuit. At each stage in the process, from hardware design language description through silicon hardware, the integrated circuit must be extensively tested for bugs and to improve performance.
While this intensive procedure may be warranted in the case of a microprocessor or other chip which is likely to be sold in high volumes, it may not be justified in the case of integrated circuits having more limited applications, such as "system on a chip" integrated circuits which include multiple complete hardware functionalities such as CPUs, ATMs, and possibly MPEG-2 decoders. Thus, it would be desirable to find a way to improve the ease with which new MPEG-2 decoder integrated circuits are designed and brought to market.